The present invention relates to a semiconductor memory device formed on a semiconductor substrate and a manufacturing method thereof.
Semiconductor memories are broadly classified into RAMs (Random-access Memories) and ROMs (Read-only Memories). Of the semiconductor memories, those used in the largest amounts as work storages for computers are dynamic RAMs (hereinafter, referred to as DRAMs).
In the DRAM, a memory cell for storing information is composed of one storage electric capacitor and a transistor for reading charges stored in the capacitor. Of the RAMs, the DRAM is composed of the minimum number of elements, and therefore, it is suitable for large-scale integration. Accordingly, such semiconductor memories have been produced on a large scale at relatively low costs.
This DRAM loses information stored therein after an elapse of a certain period of time because charges stored in the electric capacitor are canceled by thermal excitation charges generated in the semiconductor substrate or collision ionization charges due to a strong electric field. The thermal excitation charges and collision ionization charges constitute a leakage current. For this reason, the DRAM is refreshed for restoring the charges before the DRAM loses the information stored therein. In general, the refreshment is performed at intervals of about 100 ms. The reason why the semiconductor memory of this type is called the dynamic RAM is due to such an operational mode.
In the DRAM, to avoid the above leakage current, internal noise accompanied by operation, and disturbance caused by xcex1-particles, it is substantially difficult to set the level of the storage electric capacitor at a specific value or less. In other words, there exists the minimum signal charge quantity which is, depending on the integration degree of the memory and the configuration of the memory array, estimated to be equivalent to electrons of about a million pieces for a 16 Mbits DRAM and about a hundred thousand pieces for a 16 Gbits DRAM having an integration degree being 1000 times that of the 16 Mbits DRAM.
In particular, the above leakage current is generated at a pn-junction between the source or drain and the semiconductor substrate. This is because one electrode of the storage electric capacitor is connected to the source or drain of the transistor for reading. Although an actual DRAM product suppresses the collision ionization current due to an electric field by making the pn-junction as fine as possible and making gentle the gradient of an impurity concentration, it is impossible to eliminate the leakage current as is apparent from the electronic principle of the semiconductor.
Another problem of the DRAM is that the memory cell has no amplifying effect because information is stored as a quantity of charges and the charges are read out as they are, and accordingly a signal voltage is generally small and the readout rate becomes low.
The RAM includes a static RAM (SRAM) paired with the DRAM. In general, a memory cell of the SRAM is composed of six transistors, or two resistors and four transistors. These elements constitute flip-flop. The SRAM keeps the storing state insofar as it is applied with a current, and therefore, it does not require refreshment, differently. from the DRAM. The SRAM, however, has a size being several times that of the DRAM because the memory cell has a number of composing elements, and accordingly, it is relatively expensive. The SRAM enables high speed operation by an amplifying effect of the memory cell and does not require refreshment, and therefore, it has an advantage in terms of realizing ultra-low power consumption.
Meanwhile, a usual nonvolatile ROM stores charges by allowing a tunnel current to flow in a storage node surrounded by an insulator. The charge quantity is equivalent to electrons of about a hundred thousand pieces. The insulator generally has a thickness of about 10 nm or more for keeping the memory holding time for 10 years or more. The nonvolatile ROM requires a longer write time as compared with the RAM, and therefore, it cannot be used as the RAM. Further, a current is forcibly applied to the insulator by repeated writing operation, so that the insulator is gradually deteriorated and finally it is converted into a conductor layer, which makes it impossible to hold the memory. Accordingly, in an actual nonvolatile ROM, the number of writing operation is limited to a hundred thousand times.
In this way, the DRAM, SRAM, and nonvolatile ROM have advantages and disadvantages, and are used in accordance with manners most suitable therefor, respectively.
The present invention provides, as described above, a memory having both the features of the usual RAM and nonvolatile memory. The gist of the present invention is to write information in a memory node via a tunnel insulator and to read information from the memory node via a transistor using the memory node as a gate. With this configuration, there can be realized a memory exhibiting an information storing operation similar to that of the usual nonvolatile memory in combination with an amplifying function of a memory cell similar to that of the usual SRAM.
In other words, an object of the present invention is to provide a semiconductor memory device having a good long-term memory holding characteristic in combination with a stable and high speed RAM operation. Another object of the present invention is to provide a method of manufacturing such a semiconductor memory device.
To achieve the above object, a memory cell is composed of, for example, a transistor for writing which is connected to a memory node, and a transistor for reading, which uses the memory node as a gate. This will be described in detail later with reference to preferred embodiments. At this time, a first word line can be connected to the memory node. The transistor for writing can be constituted of a transistor in which a substrate structure having barrier layers, composed of a stack of barrier substrates and barrier layers, is used as the substrate of the transistor and a second word line is used as a gate.
With this configuration, since the memory node is not connected to the silicon substrate, a leakage current does not allow to flow from the silicon substrate into the memory node, differently from the memory cell of the usual DRAM. Further, since the barrier layers as insulators are present between the memory node and the source connected to a data line of the transistor for writing, it is possible to suppress, differently from the memory cell of the usual DRAM, a sub-threshold current flowing between the source and the drain of the transistor for reading and writing storage charges.
In addition, these leakage current and the sub-threshold current lose the memory of the DRAM. For this reason, as described above, the DRAM is refreshed. In general, the refreshment is repeated at intervals, of about 100 ms.
In the structure of the present invention, after the power supply is perfectly cutoff, the word line, data line, sense line and control line are all floated, that is, become 0 V. Accordingly, in the structure of the present invention, since any leakage current is not allowed to flow from the substrate, charges in the memory node can be held by making the barrier layer sufficiently thick or making the threshold voltage of the transistor for writing sufficiently high. The structure of the present invention can be thus used as a nonvolatile semiconductor memory device. To make the threshold voltage sufficiently high, the concentration of an impurity doped in the barrier substrate of the transistor for writing may be made high.
The operational condition to prevent charges of the memory node from being erased during current-carrying to the memory can be achieved by suitably selecting a relationship between a voltage of a non-selection word line and a threshold voltage of a cell writing transistor. This enables an operation similar to that of the usual SRAM.
Depending on the degree of suppressing the leakage current and the sub-threshold current within the above operational condition, the inventive memory can be realized as a semiconductor device having a characteristic changeable between that of the perfect nonvolatile memory and that of the usual DRAM. In the case of no barrier layer, the inventive memory requires the refreshment like the DRAM, and in the case where the barrier layer has a thickness comparable to that of a flash memory which is one kind of the nonvolatile memory, there can be realized a nonvolatile memory. Accordingly, the present invention has a large advantage that a desired function can be obtained by selecting the material of the barrier layer and its. thickness, and also selecting the material of the barrier substrate and its impurity concentration.
For example, in the case where the thickness of the barrier layer of the inventive memory is made thin, a sub-threshold current is allowed to flow; however, the magnitude of the sub-threshold current is smaller than that in the usual DRAM because the sub-threshold current can be somewhat suppressed in the inventive memory, and therefore, the inventive memory can act as the usual DRAM in which the time interval of refreshment is made sufficiently longer and thereby a standby power can be reduced. The reduction in standby power enables backup using a battery or the like, and accordingly, the inventive memory can be regarded as a pseudo nonvolatile memory from the viewpoint of the entire configuration including the battery.
On the other hand, an actual large-scale memory can be realized by arranging a plurality of the memory cells in a matrix, and connecting them to each other by the control line, sense line, data line, first word line, second word line, and the like.
The basic structure of one example of a memory device of the present invention has a memory cell, and a data line, word line and a sense line connected to the memory cell.
The memory cell has a memory node for storing charges, a writing element as a path for injecting or discharging charges into or from the memory node, and a reading element for detecting a charge storing state of the memory node. The reading element has a first transistor whose threshold value is changed depending on the charge storing state of the memory node, and the sense line is connected to a source/drain path of the first transistor. The writing element is disposed between the memory node and the data line, and it has a second transistor having a stacked structure of insulators and semiconductor layers and a control electrode formed on the side wall of the stacked structure. Further, the word line is connected to the control electrode.
Here, the first transistor can be formed on the substrate and the second transistor can be formed on the first transistor. That is to say, when the layout of the substrate plane is viewed from top, the configuration of the first transistor and the configuration of the second transistor are partly or entirely overlapped, and accordingly, the chip area can be reduced.
At this time, the first transistor is constituted of a field effect transistor, and a gate of the field effect transistor can serve as the memory node. A second control electrode can be provided on the side wall of the gate electrode via an insulator. In this way, the control electrode can be provided on the side wall of the memory node or the transistor. That is to say, the control electrode can extend along in the direction perpendicular to the substrate plane or along a plane crossing the substrate plane.
According to another example of the present invention, there is provided an apparatus having a MISFET (Metal Insulator Field Effect Transistor), and a stacked structure including insulators and semiconductor regions, which structure is connected to a gate connected to the MISFET. In this example, information is written or erased by injecting or discharging charges into or from the gate via the above stacked structure, and information is read out by means of a sense line connected to a source/drain path of the MISFET. The MISFET is a detecting transistor, and the gate thereof serves as a memory node. The stacked structure connected to the memory node acts as a barrier for controlling injection or discharge of charges into or from the memory node.